The Design And Verification Of DFT Integration Of High Speed Interface IP Cores For High Performance CPU

Currently, in order to accelerate the efficiency of chip design and shorten the design cycle,reuse of IP (Intellectual Property) core is the trend of SoC(System on Chip) design. Particularly,the reuse of high-speed interface IP cores, because their internal structures are not clear, only asa black box and reducing testability, which is a great challenge to the integration and verificationof DFT(Design For Testability) of high-performance CPU.The paper mainly focuses on high-speed interface IP cores for the high performanceCPU(FX chip), including high-speed serial interface hard core, such as PCIE2/SATA2/USB2PHY, and high-speed parallel interface soft core DDR3PHY, and what we have done is that theDFT functions of IP cores themselves, including JTAG (Joint Test Action Group) and BIST(Built-In Self Test), are verified and analysed. After integrating them into the entire CPU, thesame work has been done. Then by using JTAG interface to start the BIST logic to verify theirinternal and external loopback functions. The paper analyses the DFT structures of the IP cores,and provides specific analytical methods and validation results. It shows that how to ensure thecorrectness of the IP cores themselves, how to use them to integrate effectively, and how toensure that the test codes are right.The main innovated and difficult parts are summarized in the following aspects:1) In this paper, by using the JTAG and BIST techniques effectively to verify the internaland external loopback functions of PCIE2/SATA2PHY, and it proposes a good way to verifythe analog and digital paths of these cores. In addition, the logic functions of BIST of the USB2PHY are verified, which can ensure the USB2PHY run normally at low speed, high speed andfull speed BIST mode respectively.2) I have found the JTAG instructions of the PCIE2PHY are wrong by experiments.Compared with the provided function of USERCODE and DSCAN instructions, actual functionsare that the former has implemented the BYPASS function, and actual number of DR (dataregister) bits of the latter is3209.3) Taking the irrational factors of the environment and physical design into account, whenthe frequency of the DDR3PHY can not reach800Mbps, by reducing the JTAG test clockfrequency to sample the validation data of DDR3PHY, we obtain test codes which ensure it canalso work normally in this case.At present, these work has been applied to FX chip which is being taped out. This researchcan not only ensure the functions of these IP cores’ transceiver module are correct, but also showthat such a related engineer problem can draw lessons from the methods mentioned above.