Compact JTAG Design And Verification

Increasing chip integration and the growing focus on power management have created new challenges that were not considered when the IEEE STD 1149.1 was originally developed. The purpose of CJTAG interface based on the IEEE STD 1149.7 is to define a more power debug and test interface which meets an expanding set of challenges facing debug and test systems with few pins while perserving the hardware and software investments of the many industries currently using the IEEE STD 1149.1. The CJTAG interface proivdes a scalable solution to meet the needs of varied component and system complexities according to the six TAP.7 Classes (T0 ~ T5).It has implemented a CJTAG aligned with IEEE1149.7. Depending on using DR scan way to generate the ZBS and then the control level will be come out by counting to ZBS, it improves the scan performance and is under control of power consumption on this paper. Simultaneously a reused and reconfiguration verification environment has been implemented by us, all these features of CJTAG has been fully verified by us, and then guarantee the correct implementation of these features. Currently the CJTAG IP we have designed and verified has been integrated into the formal chip, and it will be a prosperous outlook for the future application. After the function of JTAG and CJTAG has been descripted shortly, the paper mainly focuses on the design and verification parts which I have participated on the CJTAG project.