Design And Verification Of IP Cores Interconnection Model Based On AXI4

With the continuous improvement of semiconductor technology,the technology of large-scale integrated circuit designed on the System-on-a-Chip has been rapidly improved by using the reusable intellectual property cores.On-chip bus is an important method to realize the IP cores interconnection.As the newest protocol of the ARM company,AXI4 bus has the excellent overlapping transmission and scrambling transmission mechanism.Thus,it has become the first choice for on-chip bus in the industry and the research focus of the academic community.At present,the AXI4 bus IP cores interconnection models on the market are not good at communicating with low speed equipment,and usually have the low transmission efficiency.Therefore,it is of great significance to design a new IP cores interconnection model,which have the advantages of low cost,high performance,low delay and easy extensibility.The purpose of this paper is to design an IP cores interconnection model mainly composed of CPU,AXI4 bus,SPI and UART.This model was realized by designing the AXI4 host interface and three ARMv4 custom instructions.By designing the AXI4 slave interface,the deficiency of the APB conversion bridge can be overcome,and the AXI4 bus can carry out full duplex communications with multiple slave machines at the same time.Therefore,the bandwidth and data transmission efficiency of this model can be greatly improved.In this paper,the whole design was finished by verilog language,which can easily take full advantage of the parallel characteristic of FPGA.While the model carries out data transmission,CPU can execute instructions independently,thus it has a high instruction execution efficiency.In addition,this paper developed a more comprehensive target and test platform for the new model verification.By performing a large number of test procedures,this new model passed the function verification and performance test by the two aspects of Modelsim simulation and board-level verificationn.The result shows that the new model designed in this paper has the expected functions and outstanding performances,including strong practicability and stability.Compared with the similar interconnection models,this new model has the obvious advantages of strong portability,high transmission efficiency,and easy extensibility.What is more,this new modle has its own research and development authorization,the use-cost will be reduced greatly,thus it can be applied to the design of products so as to gain market profits.In addition,this paper can serve asa technical reference for domestic researchers in SoC design and verification field,so as to shorten the development of SoC products with various functions,and it has far-reaching significance for the design and verification of domestic SoC chips.