Integration And Verification Of Communication Interface In High-Speed Signal Processing System

With the development of integrated circuit technology,IP cores available for direct use are becoming more and more abundant.Designing an integrated circuit which meets market demands can be realized quickly.However,due to the ever-increasing scale of circuit systems,communication problems between IP modules have become increasingly prominent.The appropriate bus needs to be selected to achieve interconnection between the IP modules.Bus and bus bridge designs directly influence the realization of the circuit system functions.The SPI interface has been widely used in ADC chip configuration due to its simple circuit structure and reliable communication.In this thesis,the ADC chip is taken as the peripheral circuit to accept the control of the high-speed signal processing communication system.This thesis aims to design a SPI interface circuit for the configuration of the ADC and DAC chip,and design the OPB bus bridge and bus arbiter to integrate the SPI interface and other communication peripherals onto the OPB bus and can effectively avoid bus contention issues.To configure the ADC and DAC chip,a SPI circuit was firstly designed to support both master and slave mode,variable data length and adjustable data rate.The OPBtoIPS bridge was then designed,in which a multi-IP address decoding method was designed to integrate the SPI module,signal processing IP module and other peripheral communication IP cores onto the OPB bus,which realized the reuse of peripheral IP cores and improved the efficiency of bus integration.Then an OPB arbiter was designed to reasonably allocate bus resources.This design focused on an improved circular priority arbitration algorithm to effectively arbitrate the bus requests so as to avoid data transmission errors that may be caused when multiple master devices on the bus simultaneously read and write to SPI and other peripheral interfaces.On the basis of completing the hardware circuit designs of all the above modules,waveform simulations were performed.System-level board verification was performed on Xilinx's K7 series FPGA development board,with a clock frequency of 97.87 MHz and resource utilization of 53.9%.The verification results show that the SPI interface is compatible with the SPI protocol,supports 4,8 and 16-bit data transmission and supports a variable data transmission rate of up to 5 MHz.It achieves the desired goals of configuring ADC and DAC chips and can be flexibly applied to other SPI interface communication occasions.The OPBtoIPS bus bridge implements the conversion of two bus protocols and integrates SPI,UART,IIC and CAN on the OPB bus.The bus bridge also makes it convenient to add other peripherals to the bus.The OPB arbiter can efficiently arbitrate the bus request so that the bus resources are reasonably allocated.The integrated high-speed signal processing system can sample high-speed signals with a center frequency of 70 MHz and a bandwidth of 10 MHz.At the same time,it can effectively attenuate interference signals,which has practical value and practical significance.