The Research On Logic BIST Of SOC

Along with the rising of the chip size and work frequency, especially SOC appearing, the test charge increased sharply, because of the embedded cores, test data increasing and difficult to access the cores. The traditional tests off line become not to fit the IC development. So the BIST therewith its' unexampled advantage becomes the research hotspot to solve the problem of SOC testing.For using the limited resource to fill SOC test, optimizing test resource become very need. Compressing for test data is an effective method to optimize test resource. In this paper, a series of test scheme aiming at single core, multiple cores and low power test were presented after studying logic BIST. The main work of the dissertation is as below:Aiming at BIST for single core, a BIST scheme based on selecting state transition of folding counters is presented. On the basis of folding counters, LFSR is used to encode the seeds of the folding counters, where folding distances are stored to control deterministic test pattern generation, so that the generated test set is completely equal to the original test set. This scheme solves compression of the deterministic test set as well as overcomes overlapping and redundancy of test patterns produced by the different seeds. Experimental results prove that it not only achieves high test data compression ratio, but efficiently reduces test application time, and average test application time only is four percent of the same type scheme.Aiming at Low-Power BIST, a novel low-power BIST scheme was presented. On the basis of folding counters, the reseeding of the folding-seed were improved by deleting the void or redundancy testing pattern and increasing the relativity of the test vectors and parallel loading test vectors, so that the power consumption inside the circuit under testing was reduced enormously. This scheme not only decreases testing-time, but also reduces test power effectively. The average input switching activity is only 2.7% of the same type scheme.Aiming at BIST for multiple cores, a novel BIST scheme for multiple cores was presented in this paper. The test data of multiple cores was compressed and decompressed as whole. Basing on bus of the SOC, the test vectors of multiple cores are loaded by the same scan-path. This scheme can provide the testing of multiple cores at the same time. The test time and hardware overhead are efficiently reduced at one time. The compression ratio is very high about 94%, as well as the structure is very simple.The experimental results show that this scheme is a superduper BIST for multiple Cores.