Research And Design Of The High-speed Interface Based On RapidIO

The traditional interconnect bus can no long meet the requirements of the embedded processor whose frequency and performance is rapidly growing because of its lower transfer rate and of its simple system topology. In this situation, the International Embedded System Interconnect Standards Association proposed the RapidIO interconnect bus protocol, which allows wide communication rate----from1Gbps to60Gbps and supports almost every kind of system topology. Therefore, the research and design of RapidIO-based high-speed transfer interface have important practical significance for embedded system.In the beginning, the paper analyzes the function and structure of the RapidlO’s hierarchical architecture which has logical layer, transport layer and physical layer and introduces the logic operation and packet format of the RapidIO. Based on that, the RapidIO serial physical layer module is designed. Specifically, the paper gives the principles and the design schemes of the CRC block,8B/10B encoding and decoding block, serial and parallel transformation block and channel synchronization block and then discusses the speed optimization of the circuit. In order to study the application of the RapidIO interconnect bus in the embedded system, a common RapidIO interconnect application system is proposed. The system includes RapidIO module, DMA module, FIFO module and on-chip memory module, each of whose function structures and parameter settings are analyzed in the paper. After that, the testing model of the RapidIO serial physical layer and it’s interconnect application system is designed. The model verifies the read, write, string write and maintenance read and write transaction of the interconnect application system including the independent design RapidIO serial physical layer module and the system including Altera’s RapidIO serial physical layer module. The verification results are analyzed and compared and show that the independent design RapidIO serial physical layer module and the embedded interconnect application system can work well. The results also show that the performance of the independent design RapidIO serial physical layer module still lags behind of the Altera’s RapidIO serial physical layer module and needs to be optimized.