Chip Design And Physical Realization Based On SoPC Architecture

With the continuous development of information industry, a variety of electronic products emerging trend. In this era of SoC into almost all aspects of society, people made more flexible requirements for the customized SoC. They hope SoC can change in functional flexibility without adding the cost of a new flow sheet. And widely used in the field of FPGA, the FPGA performance is also put forward higher requirements. This makes SoPC in this environment born out of both its flexibility and performance characteristics have been more and more attention.SoPC is based on programmable logic devices developed hardware system, through a combination of SoC and FPGA generated, which also has the advantages of SoC and programmable logic devices, SoC provides high-performance hard-core resources for FPGA, especially CPU processing capacity, FPGA provides expansion space and reconfigurable resources for SoC. SoPC features excellent performance, scalable and programmable so that its application is very extensive, except in the course of research and development in chip design, but in communications, instrumentation and other fields have good performance. But the SoPC design method and the basic core technology controlled by foreign companies, domestic few outstanding SoPC development platform.In order to design a good performance and SoPC chip with independent intellectual property rights, this thesis adopts SoC combined with FPGA method to design SoPC. From the start, using the Godson soft-core and AMBA bus to build the SoC architecture as a whole, and mounted SDRAM controller on a bus, using some function modules, such as GMAC, to make the SoC more functionable, the logic synthesis and gate level simulation of SoC based on the simulation of the whole. After the SoC netlist verification is successful, the use of EDA automatic layout tools to complete the layout design. In the layout design process, through the rational layout of the macro module makes the standard unit ordered distribution so as to reduce congestion and optimize the timing, the position control of clock tree node to correct chip clock tree growth, and in the end, improve the layout manufacturability, ensure the layout conforms to the production standard of the foundry. Synthesis and layout design based on SMIC 65 nm process. SoC layout and FPGA layout taped out together and packaged. At the same time, design and development platform for testing the SoPC chip. The test results show that this design can meet the expected requirements of SoPC. In this thesis, a SoPC chip made based on the SoPC architecture and the domestic processor core, which is in good performace, has a variety of functions and a development platform, provides a new solution for the design of SoPC.