Low Power Physical Design Using Wireless Access SOC Chip

In the present ages, the development of VLSI design is tend to be mature, IC industry has become the footstone of the development of modern industry, It has been broad applied to computer, communication, internet and manufacturing. When the process grow to deep sub micron, power could not be ignored in IC design., it not only effect the package and cost, but also lead to the too much heat, which directly effect chip reliability. SOC design is the result of IC development. It's helpful for the circuit performance, power, cost and reliability, which has become to the direction of IC development. But with area growing, power has become to the key problem of IC design.Wireless access SOC chip is Wireless access chip, higher-layer protocol is based on the IEEE802.15.4 own develop protocol, mostly based on low power, low speed application, transmission speed is about 100Kps. This paper describes concept and methods of the implement of low power design of WirelessChip from logic synthesis to physical design, which provide a reference of implement method and flow. It can apply to other chip design to the basic of other chip design.This paper first provide an overview of low power technology development and research signification; then discusses the power distribution and optimization of all level. presents the method of low power synthesis of WirelessChip;.Based on Cadence EDA platform, implemented logic design and emphasized clock tree synthesis of low power, implemented low power physical design, floorplan phase adopt many methods for a better result, cts phase applied many ways to implemented low power design. At last this paper analyzed the power and physical verification problem of deep-sub micron process.