Since The Start Of Pre-loaded Interface Chip Design And Realization

Self-startup pre-load interface chip integrates UART serial inteface logic and control logic of access to periphery memory chips, and is used in pre-loading periphery SRAM chip after powered on, and supporting computer for programming periphery FLASH chip via com port. Self-startup pre-load interface chip was designed according to standard design flow of ASIC in short design cycle.The chip has taped out on HH-NEC 0.35um 1P3M 3V process, and is under test after COB packaged at present. Compared to implemention with FPGA, Self-startup pre-load interface design implemented with ASIC based on standard-cell has great advantage on volume, power and cost.From the point of ASIC design flow'view and in connection with the design of interface and download chip, the thesis mainly discusses: (1) partitioning and HDL Coding for synthesis; (2) logic synthesis flow; (3) physical design flow and key technology; (4) according to design specifications, the Testbench is established based on procedures and assertions, and functional and postlayout simulation are separetely done; (5) the theory and flow of Static timing analysis and Formality. Interface and download chip is control-oriented and has complex clock relationships, therefore timing design is the key and difficult point.In the end, the thesis discusses the chip's test after COB package. Basic functional test is conveniently and effectively executed utilizing software/hardware co-verification platform for the first time. However, the platform was originally developped for FPGA prototype verification, the application in chip's test can set an referential example for test task. Besides, further test is carried out using FPGA test board. The test results can tell that the chip's function is basically correct.