Back-end Of The Ethernet Controller Chip Design Technology

The thesis introduced the back-end design flow of Ethernet controller chip under the sub-micro technics, discussed and resolved the problems of the logic synthesis, physical implementation and physical verification in detail. The author accomplished not only the back-end design flow of Ethernet controller chip but also the SRAM IP integration and ESD design. In the design,"Design Compiler"and"Astro"of Synopsys Ltd were adopted respectively as the synthesis tool and APR tool. Besides,"Dracula"of Cadence Ltd was adopted as the physical verification tool.The thesis mainly fulfilled the following work:1. Integrated SRAM IP and designed the circuit of this IP. As the third party of IP, RAM integration effectively reduced the amount of time and risk of the whole ASIC design of Ethernet controller chip.2. Designed the ESD of Ethernet controller chip. In this chapter, not only the causes and dangers but also the process and model of static discharging were introduced in detail. Besides, the protection of static discharging was discussed as well. The most important thing was to analyze the design of ESD of the Ethernet cortroller chip.3. Synthesised the digital code of the Ethernet controller chip. By constraining time and area properly and analyzing various issues arising in the synthesis process, the author achieved a netlist which satisfies timing and area constraining. After the synthesis, the slack was 1.80ns, which demonstrates that the integrated Ethernet controller chip design results in line with the timing constraint requirement.4. Placement and routed of the digital part of the Ethernet controller chip according to the achieved netlist after synthesis. Many effective methods were tried in Floorplan, Placement, Clock synthesis and Routing, and the final layout of the digital part of Ethernet controller chip was presented in this chapter. After the placement and routing, the general area of the chip is 2998*1199μm 2 and the total cells is 31580.5. Finished the design of analog layout of this chip according to the netlist of the other compony. Then, the physical verification of the whole chip of Ethernet controller is finished. The problems aroused in LVS and DRC process were analyzed with proper solutions being offered. Meanwhile, the final result of physical verification was presented, which proved that the layout format file can be used in tape-out.The layout file of this program has already been used in tape-out.