Synthesis Optimization And Verification Of High Performance DSP Core

FT-66 XX is a high-performance multi-core DSP chip which developed by the National University of Defense Technology. It has fix-floating point mixed instruction and independent designed architecture for instruction set. The chip mainly used in communications technology, image processing and other embedded applications. This chip is using 40 nm process, dominant frequency design aim at 1GHz, and the on-chip storage capacity is 1MB. The performance of the internal core directly restricts the performance of the entire chip. Therefore, it is very important to do the core optimization. The main work and innovation of this paper is as follows:1. For hierarchical synthesis, the traditional setting of the constraints of the sub-module is inefficient, ineffective and other issues, so this paper presents a way to automatically extract exactly constraints out from the top with perl scripts, which makes the setting of the constraints of the sub-module be time success. Without any iteration you can get a very good synthesis result. It greatly improves work efficiency.2. In this paper, Physical Synthesis methods were studied, and achieved remarkable results. Using spg process greatly improved the timing consistency between physical synthesis and physical design. In order to improve the timing, increase controllability of the layout, and to facilitate physical design after the layout, we did some processing on layout. We put forward some solutions to handle congestion issues. In the synthesis stage, we considered the wiring of the wiring layer.3. This paper explored the optimization of the chip core in the synthesis stage. Based on the traditional optimization methods, we put forward and implemented an algorithm to do borrow time automatically. This algorithm allowed the tool doing borrow time automatically after the synthesis. It didn't need manual analysis for the timing and manual setting command. It saved human resources and improves work efficiency.4. This design used the custom trigger. We filtered the wide variety of triggers in the standard cell library, only use specific six kinds of triggers to do synthesis, and the result was not deteriorated. It not only facilitated the controlling of the trigger in physical design, but also greatly reduced the workload of the trigger custom group.5. Formal verification is throughout the design process. In this paper, formal verification problems were analyzed and solved at various stages of the design. In addition, this paper analyzed some problems found during the work and presented the solutions used in the project.At present, this chip has not been taped out yet. After using the above methods to optimize the internal core, the setup time of the physical design stage has been basically meet the requirements.