Research On DTMF Chip Top-level Timing Analysis And Optimization Design Method Based On Interface Logic Model

With the advent of ultra-large scale integrated circuit design into the deep submicron era,people have benefited greatly from daily life and work due to the great improvement of chip functions.at the same time,due to the continuous reduction of feature sizes,the physical design of chips has also become more and more complicated,and the time-consuming of physical design has also become longer and longer.In order to improve the design efficiency,the time consumption for chip design is continuously decreasing,but the scale of chip design is getting larger and larger,and more and more people begin to pay attention to reducing the time consumption for physical design.Therefore,there is an urgent need to provide a method that can improve the efficiency and competitiveness of physical design.Aiming at the front-end design data of a dual-tone multi-frequency signal transceiver chip designed by the author's company,the hierarchical physical design method based on the interface logic model is studyed by cadence's digital back-end physical synthesis tool innovus.Compared with the traditional flattening physical design,the design time consumption is reduced significantly by it.Firstly,based on the analysis of DTMF chip architecture and design specifications,the physical implementation and static timing analysis of the chip are completed based on the flattening physical design.Secondly,the method of design planning is used to separate the results_conv and tdsp_core modules from the original flattened physical design and implement them physically.The interface logic model of the two physically implemented modules is created.The interface logic model is transferred into the top layer to implement the physical implementation of the overall design.Finally,the two modules are assembled with the top layer to complete the physical design and static timing analysis of the entire chip.The comparison and analysis of design verification and results show that under the condition of 100 % time closure of physical design and design verification,the time consumption of hierarchical physical design based on interface logic model is reduced by 16.7 %.The research results show that compared with the traditional flattening physical design,the design time is shortened,the design cost is reduced,and the efficiency and competitiveness of physical design is improved by the hierarchical physical design method based on interface logic model,which has certain reference value for designers engaged in chip back-end design.