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Study And Design Of Vernier Time To Digital Converter

Posted on:2013-06-21Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y TianFull Text:PDF
GTID:2268330392468931Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of science and technology, there is a higherrequirements for precision time quantitative. While the traditional quantitativetechniques based on clock ticks have been unable to meet the demands of people. Atthe same time, the continuing development of microelectronics technology and theresearch of tapped delay line theory made the TDC appear to the world. Because offine-resolution, especially for picoseconds resolution, TDC is not only applied tohigh-energy physics, pace science, aerospace and other high-tech fields, but alsoopening up new ideas for the design of high-speed low-power ADC,high-performance frequency synthesizer in the analog IC field. Therefore theresearch of fine resolution TDC is of great significance.This thesis systematically summaries the performance of different TDCstructures. Based on the comparison, as for high-resolution and large dynamic range,Vernier ring TDC is selected to finish study. In the thesis, the basic theory ofVernier ring TDC is researched first, then Verilog-A is used to model the systemstructure to verify the overall function. According to the model simulation resultsand the analysis of calibration of non-ideal factors, a series of key modules aredesigned. The circuit includes a pre-logic unit to fulfill the identification andorientation function of the signal, avoiding the error catching up. A totallysymmetric, self-reset function time comparator is designed to achieve compareperiodic signal. The small phase error detector and redundancy circuits areemployed to solve pseudo-phase and counter error. Register bank and‘001’detection array are adopted to fake out asynchronous thermometer code and thebubble effect. A self-calibration circuit using dual-DLL is also introduced toovercome the delay varies during time quantizing process.The designing and simulation are based on0.35μm3.3V CMOS technology.All the modules as well as the whole system are simulated in0.35μm3.3V CMOStechnology. The simulation results have showed: the Vernier ring TDC conversionresolution is13.5ps and the dynamic range up to more than190ns. The resultindicates that the system meet the design objectices, that’s to say target isaccomplished.
Keywords/Search Tags:time quantitative, vernier ring, time to digital converter, Dual-DLLcalibration
PDF Full Text Request
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