Research On The Key Technologies Of Low Power 2GS/s 11b Time Domain ADC

With the reduction of CMOS feature size and the decrease of power supply voltage amplitude,the switch speed is increased at the expense of the dynamic range of analog voltage signal,and the signal-to-noise ratio that can be realized in the voltage domain is getting lower and lower.In fact,the current CMOS technology has entered the deep submicron system,and the voltage resolution can be surpassed by the time edge resolution.In the current ADC architecture research,it is a new research trend to convert the analog voltage signal in the voltage domain to the digital pulse width signal for processing.Time domain ADC gives full play to the advantages of switching speed in nanometer CMOS process,and under the same speed and accuracy,the area and power consumption of time domain ADC are incomparable to that of traditional voltage domain ADC.However,at present,the performance of time-domain ADC completely depends on high-speed transmission gate to achieve high-speed and high-precision ADC,which fails to break through the bottleneck of technology and structure.There is still no good solution for ADC with a sampling rate of more than 10 bits at GS/s,which makes it not suitable for current radar system or communication system and other high-tech fields.In view of the problems existing in the current time domain ADC,this thesis proposes an innovative two-step ADC design scheme of voltage domain time domain hybrid structure and takes advantage of the time domain variable gain of the time domain ADC,that is,without reducing the accuracy of the second stage,the redundant amplifier unit used in the traditional voltage domain two-step ADC is cancelled,which effectively solves the redundant amplifier unit The capacitor mismatching and common mode shift effect of the system give full play to the advantages of small area,low power consumption,high speed and high precision in time domain.The time interleaved technology is employed to further improve the speed of the whole ADC,and the simulation of the whole ADC achieves the excellent performance of 2GS/s 11bit under the UMC 28nm process.Some non-ideal factors in time-domain interleaving are analyzed and explained in detail.A multiplexing ring oscillator structure is proposed to reduce channel mismatch.In addition,the thesis improves many non ideal factors in the traditional time domain ADC,designs a high linearity voltage time converter circuit with capacitor bottom plate sampling and a low bit error rate time digital converter circuit with high resolution clock.Finally,other circuits suitable for this design,such as low harmonic distortion gate voltage bootstrap switch circuit,high-speed comparator circuit,multi-channel clock generation circuit and high-speed digital code readout circuit,are also described in detail.The design of this thesis strictly follows the design process of the analog-to-digital hybrid integrated circuit,from the determination of the system framework and indicators to the design and pre simulation of the unit circuit module,and then realizes the design and pre simulation of the overall circuit,and finally draws the layout and post simulation.The prototype chip is designed in a standard 28nm CMOS process with an area of0.13mm~2.Using a 1.2V supply,the ADC achieves an average power consumption of 19m W.The proposed ADC achieves 61.3 d B SNR and 70.1 d B SFDR to 100MHz frequency at2GS/s.