Design Of High Resolution Time To Digital With Digital Circuit

Along with the development of intergrated circuits, more and more applicationimplement digital circuit that is higher intergration and shorter design cycle. It has ahigher request to the precision of converter, converting speed and power consumption.Thus a new conversion processing technology, namely change the voltage domain ofsignal processing to the time domain of signal processing, is created. And time todigital converter arises at the historic moment.In this paper the proposed time-to-digital converter is gated ring oscillator timeto digital converter that applys the technology of oversampling. And the gated ringoscillator time to digital converter has a simple circuit implementaiton and gain thefirst-order noise-shapping of quantizing error and mismatch without calibration.Firstly, the basic principle of time to digital converter is introduced. And thetopology structure and working principle of serveral kinds of main gate delay time todigital converter and sub-gate delay time to digital converter are discussed. Thenaccording to their shortcomings, gated ring oscillator time to digital converter basedoversampling is proposed. Second, the main factor affecting first-order noise shapingcharacteristic is skew error. The model of skew error is established. And a testbanchof circuit simulation is used to validate the model and a method to reduce skew erroris gained. Combined the method and serval circuit structures of oscillator improvedfrequency, multi-path gated ring oscillator is proposed. The skew error of multi-pathgated ring oscillator is analysised. Then a phase processing technology based registeris leaded from a simple technology based counter. According to the applyment ofsimple gated ring oscillator, the applyment circuit structure to complex multi-pathgated ring oscillator with addressing the various obstacles. Then the overall systemarchitecture of gated ring oscillator time to digital converter is given. Finally, thelayout and simulation results of gated ring oscillator time to digital converter arepresented.The schematic and layout is designed by using SMIC0.18um standard CMOStechnology. The dynamic proposed multi-path gated ring oscillator time to digitalconverter is0.2-45ns, and the resolution is5.5ps, the nominal sampling rate is50Msps. The area of the core circuit layout is350μm×390μm and the area of thewhole layout is840μm×850μm.