Design Of A High-precision Time-to-Digital Converter Based On DLL Control

The TDC is a a kind of data converter circuit, it measures the time interval between the two input pulses, and output the digital quantitative value close to the actual time. It has been used in a wide variety of applications including digital phase-locked loops (PLL), round trip duration of a laser pulse in 3D imaging and Time of Flight (TOF) of particles in nuclear science experiments, so it strongly supports the development of 3D imaging technology, and is of great significance in military and civilian fields.Because the TDC array architecture limits the TDC's area, power consumption and requires its high resolution and wide input range, those existing TDCs which can achieve sub-gate delay resolution are difficult to extend to TDC arrays. In order to realize the wide-range, high-precision TDC which can apply to the array, the proposed TDC is improved on the classic two-level TDC. For the two-level mode structure, in the high-level TDC, asynchronous subtracter is added in front of the lowest bit of the original LFSR counter, in the realization of wide range and further limiting or reducing power consumption at the same time; while the control voltage is obtained by the DLL to improve the performance of the middle-level TDC; Finally, the double loop structures are introduced in the low-level TDC, so that the proposed TDC breaks through the smallest gate delay of the digital circuit and realizes the high precision through controlling and changing the phase of the double loop structures. Compared with the other three-level TDC, the designed TDC not only gives consideration to both precision and wide range, but also is suitable for array application. The theoretical research and correlation analysis showed that, this designed TDC is based on Dual-DLL architecture, with obvious advantages in terms of suppressing clock jitter or phase noise of ring oscillator frequency.Fabricated in TSMC 0.35?m CMOS technology, the proposed TDC is verified by Cadence EDA tools to complete the entire circuit's pre-simulation, layout, post-simulation and tape-out. Measurement results show that:under the conditions of the input clock 125MHz, this 13 bits TDC achieves an input range of 4.501?s, 547ps resolution and the maximal absolute error is 9ns. In addition, the measured accuracy of the minimum time bin is lower than 0.645LSB DNL and 1.35LSB INL.