Research Of High Speed Time Measurement Circuit Based On The Minimum Gate Delay Technology

In the past few decades,the integrated circuit technology has been greatly developed,the size was become smaller,the integration was become higher and the power consumption was become lower,it had make great contribution to the integrated circuit design.With this development,time to digital converter(TDC)has also been greatly improved in the integration,chip area,working speed,power consumption and measurement accuracy.In aerospace,laser radar and high energy physics areas has important applied by TDC.Therefore,it is very important to design high precision TDC.In this paper,different TDC structures performance were analyzed.The vernier delay chain TDC was used,it achieved high resolution and wide range of measurement.At the same time,the TDC start and stop control signals were analyzed,the external signals was not used directly control,as a result of it has relatively long and increased the gate delay time,thereby reduced the accuracy of TDC.The relationship between different rising time step signal and delay time in gate were analyzed,with the rising time become shorter and the delay time also become shorter,the TDC control signals were designed by internal voltage comparator.In this way,the original TDC precision was improved.The overall framework and timing diagram of TDC were designed and analyzed.The voltage comparator circuit,oscillator circuit,Arbiter circuit and 16 binary counter circuit were designed in the TDC circuit.The TDC start and stop steep step control signals were generated by voltage comparator circuit;the TDC vernier delay chains were generated by two oscillator circuits;the two signals which had 5ps phase of difference were accurately judged by Arbiter circuit;the TDC time measurement range was extended by 16 binary counter circuit.The error transfer model and inverter unit delay model were analyzed in TDC circuits.As TDC high speed work may be caused output error or missing code phenomenon,therefore,the input redundancy elimination circuit,pseudo "01" elimination circuit and counter anti jitter circuit were designed.Finally,the influence of errors were analyzed,direct and indirect correct methods were presented for TDC calibration.Finally,the TDC circuits using in TSMC 180 nm process and simulation with tools of Cadence Spectre,TDC resolution is 5.3ps,the power consumption is 6.5mW,the territory area is 0.13mm2,the dynamic range is 7.2ns.The results show that TDC has a good performance and achieve the expected target.