High-Precision Hybrid Time-to-Digital Converter Based On Residule Time Amplification

The 3D imaging system establishes a depth image of the target contour through distance detection.A typical imaging system can achieve the resolution with sub-millimeter level.The Li DAR system with highly sensitive SPAD sensors can generate two asynchronous rising edges to define the photonic time of flight(ToF).ToF is measured and encoded by time-to-digital converter(TDC).The code stream is processed to construct the depth image.The performance of TDC directly determines the capability of 3D imaging system.The resolution and scale of TDC determine the measurement accuracy and range of the 3D imaging system.TDC dead time limits the oversampling frequency,thereby affecting the quantization noise.An all-digital hybrid TDC circuit is proposed based on the direct ToF measurement method aiming at the wide range and high-resolution requirements for ToF measurement in the Li DAR system.Multi-segment structre is utilized to promise wide-range mearsement and a new structure which combines digital time amplifier and Vernier loop TDC is implemented to achieve high resolution.The reference clock and control voltage of the hybrid TDC are provided by the dual-loop DLL.Oversampling is utilized to decrease quantization noise.In this paper,the hybrid TDC uses a three-segment structure.Time period is firstly roughly quantized.Then middle and low TDC segments are utilized to encode quantization errors of the initial and final phases successively.The coarse quantization is completed by counter circuit,and the high-level quantization error generated afterwards is converted by the corresponding initial and final phase TDC using interpolating method.The multi-phase clocks are provided by the dominant DLL in the dual-loop DLL.In order to reduce the quantization error of middle-segment TDC,the DFF of the synchronizer uses the sensitive amplification amplifier structure and the holding time is modeled and optimized.Low-segment TDC determines the resolution of the hybrid TDC.The cascade of time amplifier and Vernier ring TDC is proposed to optimize low-segment resolution which is inversely proportional to the magnification of time amplifier.Low-segment timing constraint ensures that the low TDC has correct functions.At the same time,in order to lower the quantization noise of the low-segment TDC,a digital time amplifier is used to ensure the linearity of the magnification in the entire range.The circuit optimization in this paper is based on the proposed quantitative noise accumulation model.The circuit design,layout design and test is based on TSMC 0.18?m standard technology.The total circuit area is 1121?m×1165?m.The analog power consumption is 16.3 m A,the digital power consumption is 8.12 m A.The chip test results show that under the condition of 240 MHz input reference clock,1.8 V supply voltage and27 °C,the resolution of the proposed TDC is 39 ps,the measurement range is 508 ns.DNL is less than 0.65 LSB and INL is less than 0.975 LSB.Deadtime is lower than 1451 ns.