Research On CMOS Time-to-Digital Converter In Deep Sub-micron CMOS

Having been functioning in a time-of-flight measurement system for decades,time-to-digital converters(TDC)are increasingly demanded since the advent of all-digital PLLs(ADPLL).Technology scaling shortens the delay of logic gates,endowing delay-chain TDCs' applications in more and more systems.However,the intra-die mismatch(within die mismatch)limited its resolution and linearity.The oversampled TDCs based on Gated-Ring-Oscillator(GRO)can overcome the mismatch problem and are well suited for wide dynamic range and high resolution.But GRO-TDC suffers from the time skew error caused by the leakage and charge redistribution in the parasitic capacitors of the oscillator delay cells.The time-skew error can increase the grated in-band noise of GRO-TDC and cause the deal-zone effect.A 2-0 cascade gated-ring-oscillator(GRO)based ?? time-to-digital converter(TDC)using time-skew shaping technique is presented in this paper.The proposed TDC in-cludes a ring digital-to-time converter(Ring-DTC)and a time-register based time-domain adder.By sharing the intrinsic gated-ring quantizer of GRO-TDC,the Ring-DTC has performed no additional matching requirement,calibration free and low power con sumption.By dividing the outputs of the GRO quantizer into an MSB segment and an LSB segment,the resolution requirement of Ring-DTC is further released.With the proposed time skew shaping technique,the time-skew of GRO is 1st order shaped,and the dead-zone effect is solved.At the same time,2nd order quantization noise shaping is achieved.This technique is simple to implement and well suited for low-power and wide-band applications.On the other hand,we propose a time-to-digital converter using a charge pump and a SAR-ADC.With this architecture,high time resolution is attainable by increasing the charging current or reducing the sampling capacitance.Thus,the resolution limitation in a delay-chain TDC does not exist.We propose to use a SAR-ADC attributed to its characteristics of compact structure,scalability,low power consumption,and small area.This architechture is well suited to decrease the in-band phase noise of ADPLLs due to its small area,low power consumption and picosecond-resolution.