Research On 12-bit 1.25GS/s Sub-50mW RF Sampling Pipelined Analog-to-digital Converter

With the increasingly development of wireless communication technology,especially the emergence of 5G and 6G communication standards,the demand for radiofrequency transceivers is developing with faster speed and wider coverage.With the development of GS/s high bandwidth analog-digital converter(ADC),direct RF or IF sampling has been widely used in RF receivers due to its simple structure,low-power dissipation and other advantages.Pipelined ADC has become the first choice of GS/s high-performance ADC considering its high-speed advantage.Under more advanced technological conditions,the unique advantages of the structure can be exerted to design a high-speed and high-performance ADC to meet the requirements of wireless communication spectrum measurement and oscilloscope sampling applications.However,high performance brings more stringent requirements for circuit design indicators,so it is necessary to study and optimize the existing system structure and circuit modules.Especially in advanced technology,the increase of device speed will lead to the reduction of power supply voltage and signal swing.To solve the above problems,this thesis studys and analyzes the system structure,non-ideal effect noise and key circuits.In order to meet the requirements of communication system application,a 12-bit 1.25GS/s Sub-50m W RF sampling pipeline ADC is designed in this thesis.The following key modules are mainly studied and analyzed:(1)A class AB high gain and high bandwidth operational amplifier with dual power supply is designed,which uses gain bootstrap structure and switched capacitor common-mode feedback circuit,has high-speed differential mode signal settling time and is used as an inter-stage gain amplifier.Besides the simulation of its frequency characteristics,the change of open-loop gain with output swing and closed-loop settling time are carried out;(2)The comparator circuit is optimized,and the structure of push-pull preamplifier add latch is adopted to improve the bandwidth,reduce the imbalance and signal kick back.Monte Carlo simulation is carried out for the offset voltage of the comparator.(3)The clock of the SHA-LESS pipelined circuit is accurately designed to ensure the bandwidth matching of the two sampling channels to reduce aperture error,and the bottom plate sampling is used to improve signal linearity.(4)The background calibration algorithm of inter-stage gain error in pipelined ADC structure is studied.Combined with the derived correlation formula,the inter-stage gain error in ADC is calibrated by a pseudo-random calibration signal injection.Finally,the overall performance of the ADC is simulated,and the layout design and optimization are completed.The pipelined ADC designed in this thesis is based on the TSMC28nm standard process,with an overall area of 960*920?m~2.The test results show that under the sampling frequency of 1.25GS/s,the ADC chip can get SNDR of 62.2d B and SFDR of 75.3d B when the low frequency of 14.038MHz sinusoidal signal is input.At high frequency 550.537MHz sinusoidal signal input,we can get SNDR of 58.8d B and SFDR of 67.7d B.The overall power consumption is 45.6m W.