Design Of An OTO Memory Based On Stardand CMOS Process

Based on the logical process OTP memory cell provided by eMemory, a storagedensity of1K×13bits OTP memory is designed. The memory has16bits data width, thesupply voltage range from2V to5.5V, the Maximum of access time is100ns when thesupply voltage is higher then3V, the Minimum of programming time is30μs, the activeread current is less then2mA and the typical standby current is1μA.Firstly, this paper introduced the background and the new research of the OTPmemory. Then we demonstrated the operating mechanism of the cell, analysed twodifferent kinds of array comparatively and finished the cell design.In circuit design, the working principles and design methods for each module of theOTP memory were introduced. The voltage generating module was the vital of the wholeproject, we used a bandgap reference circuit to regulate the supply voltage and got the readvoltage, meanwhile the simulation and analysis of each module were completed. Then, wefinished the layout design of the chip and completed the simulation and analysis of thewhole circuit.Finally, we analysed and solved several key problems encountered in the design flow.This paper got the memory based on5V only device CMOS technology that iscompatible with0.18μm CMOS logic process. Few papers focus on this theme have beenreported in China. The newly-designed OTP memory has advantages in cost and technicalcomplexity. At the same time, it can work on the supply voltage range from2V to5.5V.