A High Performance CAM Design Using Optimized10T-Bitcell And Novel Double Matchline

During the development of computer technology, the processing speed of microprocessor has been much faster than the main memory access speed. In order to mitigate the speed disparity between microprocessor and main memory, the most effective method is to divide the storage hierarchy by using Cache. Cache generally consists of the Date array and the Tag array which is completed by Content Addressable Memory (CAM). CAM finds the data by parallel search and is mainly used in various kinds of high speed search application. Therefore, the design and optimization of high performance CAM has very important application value and significance.In this paper, after compared with the traditional CAM cell in stability, speed and area, it is obvious that the traditional10T bitcell has the biggest advantage which uses PMOS transistor instead of NMOS transistor in comparative logic can avoid the threshold loss. Based on the above work, a optimized10T cell is proposed and then an analysis and simulation verification has been carried on the stability. The matchline structure in this paper is based on the charge-sharing and hierarchical matchline structure. Traditional matchline structure has one matchline ML, here we uses two matchlines based on charge-sharing, charging the CML and then sharing the charges with another matchline SML. After analyzing we can see that using this matchline structure can save at least50%dynamic power consumption compared to the traditional matchline structure. It doesn’t need to precharge on the bitline so that it further reduces the whole power consumption. Finally the use of hierarchical matchline technology enhances the speed performance.The simulation results show that the proposed matching line structure can save about sixty percent power consumption compared to the traditional NOR type matchline structure, significantly decrease the peak current and improve the stability.