Compensation Method Research And Circuit Implementation For SRAM PVT

As the feature size ushers in deep sub-micro meter or even nanometer ear, the power density in the circuit has increased significantly, which makes power to be the major focus in the design for IC. Due to the natural characteristic of ultra low power, the sub-threshold design has drawn more and more attention by lowering the supply voltage below the threshold voltage to save power. However, the MOS transistor demonstrates fully different features in the sub-threshold region than that in the super-threshold region, during which the circuit would be impacted even more by the process, voltage and temperature (PVT) variations. Therefore, the robustness design for sub-threshold circuit has been the major focus in this thesis.The features with the decreasing of the supply voltage have first been analyzed in this thesis, and the effects caused by PVT variations have then been elaborated exemplified by the traditional inverter. Finally, a PVT variation compensation scheme for sub-threshold SRAM has been proposed. On the one hand, the scheme can save power to the extreme extent by designing a delay detection circuit to control the supply voltage dynamically so that the whole circuit can function well under different circumstances. On the other hand, a self-adaptive circuit, which can improve the read and hold static noise margin (SNM) of the sub-threshold SRAM, has been proposed to enhance the robustness of the whole circuit.The major innovations are included as follows:The systematical SRAM compensation scheme(?)The proposed compensation circuit can adjust the supply voltage dynamically by detecting the delay variation caused by process and temperature, so that the power can be saved significantly on the premise of performance satisfied. The sirr.a’ation results show that the sub-threshold circuit can function well under500kHz frequency and the supply voltage can be adjusted dynamically from0.3-0.6V to make sure the delay to be within (0.375-0.625) us.(?)The circuit SRAM compensation schemeA circuit that can enhance the read and hold SNM has been proposed in this thesis. The proposed design can adjust the body voltage of PMOS transistors dynamically by detecting the threshold voltage variations so that the robustness of the whole circuit can be improved significantly. The simulation results show that by adopting the proposed design, the mean value of the read and hold SNM can be improved by18%and0.7%, respectively, and the standard value can be improved by82%and29.4%, respectively. Meanwhile, the proposed design can be functioned well under a range of supply voltages (0.2-0.5V), under which the read and hold SNM can all be enhanced effectively with little write SNM penalty. In order to facilitate the interconnect between sub-threshold region and super-threshold region, an amplitude-limited circuit has also been designed to connect the two regions. The corresponding simulation results demonstrate that the amplitude-limited circuit can work well even under the300mV supply voltage.(?) A programmable output LDOA programmable output LDO has been proposed in this thesis, whose supply voltage is1.2V while its output is300mV-600mV. The programmable output LDO has8levels, and each level corresponds to42.86mV. The circuit has been verified through65nm SMIC process tape-out.The PVT compensation scheme proposed in this thesis has been applied to a256×16sub-threshold SRAM and the corresponding simulation results show that this scheme can improve the robustness of the sub-threshold SRAM effectively.