Key Technology Research And Circuit Design Of Low-power SRAM Bitcell

With the progress of MOS transistor tube manufacturing technology and the extensive use of SoC system, Including:high-speed mobile network communication technology, GPS global satellite navigation technology, wireless sensor technology,etc.The low power demand of the SoC system is higher and higher. As the SoC system of large power consumption, therefore, for the memory chips in terms of low power consumption is also more and more demanding. In various memory chips used in the SoC system, because of its unique low power advantages,SRAM occupy the proportion of about70%. According to the prediction, by201494%of the total area on SoC chip will be dominated by on-chip memory. As storage chip embedded circuit, SRAM is one of the essential features, its power consumption will directly affect the power consumption of the whole SoC chip.As a result, the static memory (SRAM) of low power design got widely attention. In2005, professor Anantha chandrakasan from MIT and his team and Texas instruments association jointly put forward a new kind of low power technology: the subthreshold circuit design technology. The technology set the power supply voltage to the subthreshold area (Vdd<Vth) to achieve very low system power consumption. But, as great reduce of the power supply voltage, the environment parameter and process deviation affect the performance of the threshold circuit also changing exponentially, easily lead to deadly functional mistakes of the bitcell circuit. At the same time, as the great reduce of the supply voltage because of the bitcell of the SRAM is at a high density integration, the static power caused by the leakage current could not be neglected too.Traditional6T SRAM bitcell usually do read and write operations on data in a storage node through two bitlines. The read operation will produce certain effect of nodes on the data, the influence will cause read operation damage in certain situations. Especially when the work voltage drop close to the subthreshold area, stability of the traditional6T unit greatly reduced, functional errors appear easily, its stability have been unable to meet the basic requirements of normal work.Thus,to guarantee the bitcell curcuit could work at the subthreshold area,it’s necessary to do some research in the storage unit circuit design theory and the structure of the bitcell circuit. Based on that some new bitcell circuit design should be carried out.On the traditional6T bitcell limited reliability problems under the subthreshold voltage. In this paper, a new type of8T SRAM bitcell structure is proposed.Aiming at the read operation having influence on data storage node under the threshold voltage, this paper puts forward an SRAM bitcell structure of reading and writing separation technology, reducing the area loss as far as possible under the premise of good noise tolerance.At the same time, on design of bitcell, noise tolerance and the static power consumption and dynamic power consumption has certain contradiction, there is a corresponding description in the text too.