Research And Design Of Low Power Pipelined ADC In 65NM CMOS Technology

As required by System-on-a-Chip (SoC) integration and state-of-the-art CMOS technology, analog supply voltage is forced to decrease, following that of the digital part. Meanwhile, handset equipments will impose stringent requirement on power consumptions. And analog-to-digital converter (ADC) is key design block in modern mixed-signal processing system as the interface between actual analog signal and digital processing. With the CMOS process technology continuously scaling down, inherent frequency of MOSFETs is increased. On the contrary, the inherent gain degradation and low supply voltage limit the performance of analog circuits. Therefore, the design of low-power high-performance ADC in deep sub-micron CMOS process becomes a major challenge.Based on the background of LTE mobile communication applications, this paper is needed to design a 10bit resolution over 100MS/s rate and more than 9bit ENOB pipelined ADC in SMIC 65nm CMOS Logic process. In the beginning this design introduced the performance parameters and main sources of nonlinearity error of pipelined ADC. Based on the analysis in power, lots of commonly used low power design methods are discussed. The traditional SHA is removed to reduce the power consumption. And the op-amp sharing and capacitor sharing techniques are used to save more. After that, some transistor level circuits are designed through analysis and optimization, which are confirmed by simulation. Finally, the layout design is completed in this pipelined ADC. In the post simulation, this work can achieve 9.8 ENOB in 150MS/s and 23MHz input signal, which especially has 78dB SFDR and only consumes 22mW.The achievement of this work provides lots of useful comments and a good reference on the design of analog circuits and layout in sub-micron process, especially in nanometer process. And this paper makes a certain exploration for low-power ADC designs, such as op-amp sharing and capacitor sharing technique.