A Design Of BRAM For FPGA

With the development of integrated circuit design technology, the demand of amemory with high speed and low power consumption increases significantly. ABlockRAM is designed with the SMIC0.12μm craft based on analyzing thearchitecture of virtex II FPGA, especially on memory cell, sensitive amplifier andperipheral circuit.In the paper, a dual ports memory with8T SRAM cell is designed. The StaticNoise Margin of the memory cell is about515mV. The anti-noise ability of thememory cell is1.27times to6T SRAM under the condition of the same size. Thestructure of traditional sensitive amplifier is optimized by including the chargingcircuit and balance circuit. After optimization, it only takes176ps to read or write dataand the speed is about2times faster than the traditional sensitive amplifier. The majorperipheral circuit of BRAM is designed and analyzed by adding the small pulse controlcircuit in reading and writing control circuit, the width of the small pulse can bereached to0.842ns. The small pulse signal is used as the memory internal clock caneffectively improve the stability of the reading and writing circuit.In the paper, the function of the BRAM is simulated with NC_verilog andnanosim. The results show that the dual ports memory in the design can be configuredinto multi modes, such as reading and writing, only read or only write operating mode.Lots of simulation results show that the dual ports memory in the design has highperformance and can be worked stably in FPGA chip with10million gates.