Design Of Multiplexing Circuit Of Sensitive Amplifier And Sigmoid Activation Function Generator

The Sense Amplifier(SA)is a key module in the reading process of the SRAM(Static Random Access Memory).It determines the time,power consumption and accuracy of the SRAM reading process.With the in-depth integration of SRAM in-memory calculation and neural network,the problem of single function and large area overhead of the sense amplifier has become more and more prominent.At the same time,the complex hardware implementation of the Sigmoid activation function in the neural network is also a difficult point in the design of the neural network's in-memory calculation.In order to solve the above problems effectively,a circuit design of multiplexing a sense amplifier and a Sigmoid activation function generator is proposed in this paper.The main contents are as follows:In this paper,the background,current situation and trend of in memory computing are described firstly.Then,the simple mathematical models and advantages and disadvantages of voltage latch sense amplifier(VLSA),current latch SA,sigmoid,tanh and relu are analyzed in detail.The existing technology of two kinds of sigmoid activation function generators is discussed emphatically.Finally,based on the above analysis,a multiplex circuit design based on TSMC 65 nm and sigmoid activation function generator is proposed.By adding three PMOS transistors to the circuit of the traditional sense amplifier,the designed circuit can realize two working modes,namely,the working mode of SA and the working mode of the Sigmoid activation function generator.Under the action of the control signal,the circuit can be switched back and forth between the two working modes,so that there is no need to add an additional Sigmoid activation function generator circuit in the hardware design of the SRAM-based neural network inmemory calculation.The circuit not only has a simple structure,but also simplifies the hardware implementation of the Sigmoid activation function generator while enriching the functionality of the sensitive amplifier and reducing the cost of the in-memory calculation chip area.