The Synthesis Implementation And Verification Of Bluetooth Chip

The methodology of IC design needs to be improved with the developing of IC technology and the increasing of scale of IC. In DSM process, there are two major factors affect the IC backend design. One is the timing problem, the other is the signal integrity problem. They are caused by increasing interconnection delay in circuit delay and decreasing of the wire spacing and power supply voltage. How to forecast and represent exactly the effect of DSM process requires a well structured backend design flow that can be easily used and reused.The paper firstly analyses the principle of optimization of combinational logic and sequential logic, and do logic synthesis of Bluetooth chip with BlastCreate, and there is no setup timing violations, and the synthesis constraint is established on the construction characteristics of Bluetooth chip. Then introduces elaborately the flow of layout with BlastFusion, which includes floorplan, power/ground plan, placement, clock tree synthesis and routing, and also introduces the strategy of floorplan and routing, and determine the die area which is 8.4 square millimeters. Finally, the paper investigates three back-end verification technology in detail, which are equivalence checking with Onespin 360 EC, STA with PrimeTime, and layout verification with Calibre. The verification results show that netlist correctly implements chip function of RTL code, and there is no setup, hold and transition timing violation, and physical implementation satisfies design rule as well as interconnection.