| The semiconductor process technology regularly provides newer techniques and recipes that allow fabricating smaller, cheaper, and faster transistors in integrated circuits (IC). Nevertheless, it is up to the IC design and optimization techniques to fully employ the opportunity to build faster, more complex electronic systems within a reasonable cost.; In recent years, computer-aided design (CAD) tools have been unable to effectively handle the new design issues and effects arising in fabrication technologies with deep-submicron (DSM) resolution. Consequently, the semiconductor industry has experienced a productivity gap between its fabrication and design capabilities. DSM technologies are forcing the philosophy of design to shift focus from transistors to interconnects and, as a result, many CAD techniques have to be fully re-designed or significantly altered to tackle the new technology constraints.; The increased importance of interconnet delay and area in IC synthesis forces design flows to no longer be divided into two artificially separated phases known as front-end and back-end. MERLIN and *SiMPA are two new algorithms, each integrating a set of logic and layout synthesis steps into a unified dynamic programming based solution. MERLIN integrates fanout optimization and global routing, whereas, *SiMPA integrates floorplanning, technology-mapping, and gate placement.; The concerns regarding the implementation of these unification-based algorithms have been studied in PEGASUS, an environment for specifying, synthesizing, and optimizing large designs. PEGASUS provides the facility, i.e. combined logical and physical database and utilities, for implementing application programs for integrated logic and layout synthesis. This CAD software package has been designed according to object-oriented programming principles and is intended to be efficient, programmable, and extensible. |
