Research And Realization Of Combinational Logic Synthesis In VHDL High-Level Synthesis System

With the developments of computer technology, CAD and EDA are growing expontionally all of the world.High-level synthesis has been developed on the base of logic synthesis. It starts from the behavioral design description of high-level and outputs the structural description with lower level as a result. So the design complexity can be simplified and design efficiency can be raised.Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description.This paper focuses on the combitional logic synthesis including two level logic synthesis and multiple level synthesis. And it is a part of control flow synthesis in a controller synthesis system. In this paper following problems are proposed and implemented:(1) Implement the algorithm "ESPRESSO", and make it suit to the system.(2) Implement the algorithm "Rectangle Cover".(3) Aimed at practical library of technology units,define the weight of factor in factoring.(4) Design and implement the alogrithm "Delay Balance in Multiple level Logic Synthesis".(5) Design the alogrithm "BDD Decomposition based on Generalized Dominator ".Additionally, we use the simulation mechanism to verify the results of logic synthesis problems discussed above,which pave the path to the future work.