The Design Of Household Appliances Multifunctional Special Chip

The developing economy and the improving people’s living standards makes the consumer electronics products have more widely used and deep into the people’s daily lives. These products make people’s lives more and more colorful and influence the people’s lifestyles and buying habits. Currently the world’s consumer electronics market development process is product innovation, falling prices, increased demand product update, which makes the consumer electronics products toward the direction of development of digital, integrated, intelligent and networked, while strengthening the work of the modular and standardized, so that the functionality of consumer electronics products more perfect, and toward the low-power, low cost, small size and direction of evolution. Through researching and analysising of the common household appliances control circuit, and based on the many problems in practice of the commonly used structure as well as the market demand, Author designs a multi-functional household appliances dedicated chip, which has a very important practical value in reducing small systems in particular, the size and cost of the product of small household appliances.Using the top-down design methodology, this paper completed the design and implementation of the whole process of the household appliances multifunctional special purpose chip design. According to the analysis of the control structures of household appliances, author points out the main problems of this structure, and on this basis, complets the design of the functional structure of the paper, then using Verilog HDL hardware description language to complete the RTL description of the system. Completing the RTL-level design, author uses the Synopsys VCS (Verilog Compile Simulator,) a dynamic simulation tool for design, and contrast the simulation results with the functional requirements to prove the correctness of the design. Completing the functional verification, author uses logic synthesis of the Synopsys DC (Design Compile) tool for design, analyzes a detailed account of the basic concepts of logic synthesis, and run the preparation of the design area and timing constraints script, and generate the reports. The process is based on TSMC’s0.13um CMOS. Completing logic synthesis, author uses the Synopsys ICC (the IC Compiler,) tools to carry out the layout of the wiring work, the paper covers the include from the layout plan to the clock tree integrated into the wiring success of each specific step of the realization principle, runs the script and layout results analysis, and complets the design of the layout work, given the map of the layout.