AUTOMATIC RANDOM LOGIC LAYOUT SYNTHESIS - A MODULE GENERATOR APPROACH (VLSI, SILICON COMPILATION, DESIGN AUTOMATION, CELL SYNTHESIS, GRID)

A new approach is introduced for solving the automatic random logic layout synthesis problem. The emphasis is on the global optimization which requires that partitioning, placement and synthesis schemes consider the two-dimensional nature of the problem. Divide-and-conquer principle is used for partitioning the logic into small cells. The placement and wire assignment scheme propagates the structural constraints of the module to the lowest level cells. Cells are then custom-synthesized under those structural constraints by the cell synthesizer. The cell synthesizer uses one-dimensional cell structures and new efficient linear-time algorithms based on the interval graph optimization for producing an optimal layout on the virtual grid and experiments layout synthesis on virtual grids under multiple structural constraints.;The effectiveness of imposing relative I/O ordering constraints is supported by the experimental data. Routing area reduction usually more than compensates for the cell area penalty. Smaller than quadratic area growth rate for cell synthesis has been observed. Experience suggests that this approach is a viable and promising one for VLSI layout synthesis.