The Design Of High-speed Data Acquisition And Storage System

Thesis designs a data-collecting and data-storing system on high frequency pulse codesignals. This system has such performances as high sampling rate, external trigger, smallroom, high impact resistance.This system has parallel dual-channel sampling alternately technique, reaching thesampling frequency of200Hz. The sampling clock of two AD channels goes through the100M clock produced by FPGA phase-locked loop, and two channels have the samplingclock phase difference of180degrees. In order to make pulse code signals match AD inputrequirements, there are the damping circuits on those signals and single-ended to differentialconversion, to enhance the signals anti-interference ability. The data from AD sampling goto the FPGA cache first, and then be written to the memory of SSRAM, to realize thesampling frequency of200M.In the design of data-collecting circuit, it needs very long signal-establishing andsignal-maintaining time, and the signal interity problems brought by high speed, such assignal crosstalk and reflection, are needed to be considered in the PCB board-designing at thesame time. Therefore, the timing constraint in the FPGA logic design, can ensure data intothe FPGA Internal registers, avoiding the metastable phenomenon happening. The severalmethods like equliong wiring and internal electrical layer segmentation about the impedancematching and key network, can ensure the high-speed sampling in the design of PCB boardThe thesis fully introduces the hardware circuit design, including the front dampingcircuits, single-ended to differential circuit, high-speed AD conversion circuit, FPGAcontrolling circuit, SSRAM memory circuit, power supply management and USB interfacecircuit. Moreover, the thesis fully analyses the key technologies of high-speeddata-collecting system, carries on the simulation and debugging, and verifies the system’scorrectness by the laboratory testing at last.