| The Field Programmable Gate Array (FPGA) has become a popular implementation medium for digital circuits due to its ability to be configured to realize a variety of different circuits. Although the configurable nature of FPGAs is very attractive, circuits implemented in FPGAs are almost an order of magnitude slower than their ASIC counterparts. Thus it has become increasingly difficult for users to realize realistic timing constraints for FPGA implementations. This is usually referred to as the “timing closure” problem.; This thesis investigates methods for achieving timing closure for FPGA based designs. Two main techniques are studied in this dissertation. The first studies the effects of creating arbitrary mappings between the logical and physical hierarchy of a design. This method has shown an average of 12% speed improvement when used to map critical sections of logic to fast physical regions on the target device. The second technique tightly integrates netlist optimizations with the placement and routing steps of the FPGA CAD flow. The circuit is restructured with a suite of timing-driven optimizations to better cope with the routing delays inherent in FPGAs. The suite of optimizations includes sequential retiming, Shannon's decomposition theorem, and clock skew optimization. Each technique is applicable, depending on circuit characteristics, or they may all be used in concert. These restructuring techniques have shown an average speedup of up to 25%. |
