Research And Realization On Matching Filter And Timing Recovery In 800Mbps High Speed Data Transmission Receiver

Data relay satellite communication is one of the main space projects of our country in recent years, among which the high-rate data transmission technology is one of the key points. With the rapid development of the space project of our country, the requirement of real-time transfer data rate from the satellite to the ground is getting higher and higher. So the development of the high-rate data transmission technology has huge significance for solving the space-to-earth high speed data transmission.This article grounds on the project of an 800Mbps 8PSK high-speed data transmission receiver and is developed from it. It studies some key technologies of all-digital receiver for 8PSK modulation and its FPGA implementation. Several subjects are discussed; including parallel receive for high-rate data, matched-filtering, timing recovery.Firstly, the whole framework of high speed digital transmission receiver is given, and it is discussed for the implement method of the framework.Secondly, the algorithm and the structure of matching filter on frequency domain are analyzed. It infers the simple structure of matching filter, also considers the relationship of speed and resource.Then, the algorithm and the loop structure of symbol timing recovery are analyzed. It also gives some kinds of timing estimate algorithm to compare based on the high speed digital transmission receiver structure.Finally, High speed data receive structure, the parallel structure of matching filter and the timing recovery loop is designed and realized in FPGA.Furthermore, the design rules of high-speed digital systems and their self-checking and testing techniques are summed up by combining the project experience and lots of application literature.