Fpga-based Radar Timing Controller Design And Realization

Radar is a complex system composed of many different modules with different functions. To make these modules work together properly,these modules must work in a certain timing coordination. The radar timing control system provides the precise timing for these modules with different trigger pulse. Modern radar system timing control mainly contains MCU, DSP, FPGA, CPLD and other types of control Integrated circuits chip. FPGA was widely used in the modern system design like Radar, Communication and Other industrial area for these properties: high precision, reliability, compatibility, scalability, easy programmability and reconfigurable, short design period, etc.Integrated circuits and system design have been great developed in modern electronic systems. The complexity and performance of these chips have significantly enhanced, these greatly impact the modern high performance electronic system, and bring new opportunities: the signal transmission speed faster and faster, more powerful data processing ability,increasing time control precision, etc. These development also brought new challenges to the modern circuit, high-speed switching and high-speed signal transmission has brought many new problems to the circuit system, signal integrity problem , power integrity problem, etc. Therefore, high speed circuit knowledge should be considered during the hardware design phase. High-speed hardware circuit design, integrated chip performance, logic coding style and connection between different modules related to the stability and quality of the modern high-speed system.This paper presents a solution of a radar timing controller based on Altera's FPGA EP3SL70. The timing controller works under the control of the host computer, generates timing control signal for the radar transmitter,receiver modules and other modules. This paper covers the following field: system level design, high-speed circuit schematic and printed circuit plate board level design, the simulation after PCB design, the FPGA coding and debugging,the timing controller board testing and system debugging.In the initial stage,complete the system level design and chips selection were based on the analysis of the timing controller and the external modules. Complete Schematic circuit design according to chip data and knowledge of the application circuit design theory after system design and chip selection.Complete the circuit board level design and simulation work after PCB design by Cadence PCB tools Allegro.Complete the logic code design of radar timing controller according to system requirements by using the state machine theory and knowledge of digital circuit.Completed the testing and debugging work of radar timing controller. The results show that the radar system timing controller can work in accordance with design requirements.