Cpri Protocol Based Fpga High-Speed Data Interface Module Design And Implementation

With the progress of science and technology, the continuous development of communication technology, and the communication technology of ongoing research work. Time Division Long Term Evolution as the research and development of communication technology standard, TD-SCDMA (Time Division Synchronization Code Division Multiple Access) the long-term Evolution of technology, our country in "New generation broadband wireless communication network" program of the TD-LTE research has made a huge investment. Ir interface protocol is the main interface protocol between the TD-LTE base station equipment and radio frequency equipment. Further study of Ir interface protocols can improve the protocol function, promote the TD-SCDMA and is of great significance in the promotion of LTE.This article in order to verify Ir interface’s processing capabilities in IQ (In-phase Quadrature) data, base station equipment need to make the IQ data parsing out by CPRI nuclear transmit to computer for short-term storage in a way of real-time and high-speed transmission. According to the functional requirements of this project, this article designed and implemented IQ high-speed data transmission module. The main work includes:adopt from top to bottom, modular design idea the overall framework of the data transmission module design; With the improved asynchronous FIFO IQ data of different clock frequencies across the clock domain synchronization, implementation rate of automatic matching of different CPRI line rate; Proposed scheme based on FPGA to realize data transmission protocol stack, UDP/IP transmission on the layered protocol stack of transport layer, network layer and data link layer protocol packets encapsulation and sends a state machine, the lower IQ data at a high speed.This article for testing base station equipment and radio frequency devices in IQ processing capacity in the process of data transmission, need to send IQ data cache, the received data real-time than IQ, comparing findings to PC. Thus, this paper design and implement high IQ data caching module, the main work includes:break through the traditional cache mathod, FPGA is presented in this paper the external DDR3SDRAM and the method of combining the internal BRAM, under the PLB bus control, realizing the IQ data cache; Using FPGA internal BRAM cache implementations for different CPRI line rate under the condition of IQ data automatically rate matching; Proposed global input clock buffer and clock design method of combining the digital clock management unit, provide reliable clock for high-speed IQ data caching module support. Use PlanAhead layout optimization design of the high IQ data caching module. Through test validation, this paper implemented by high speed data interface module, which can realize the IQ high-speed data real-time transmission and the cache function, meet the functional requirements.