Research, Based On The Fpga Airborne High-speed Data Recording System

Based on the interface technology and hardware programmable technology ,this thesis introduces a new design scheme implementing a hard disk controller in a PLD with a high speed data recording rate. It can meet miniaturized and integrated demand for data recording equipment used on the airborne standoff.The thesis has developed an hard-disk(HDD) controller in a Cyclone FPGA with lowest power, lowest cost and good performance. The controller is compatible with the ATA interface specification, and the highest data burst transfer rate between the controller and the HDD can reach 33.3MByte/s with the Ultra DMA mode 2. The controller is based on VHDL and on hierarchical Design rules. The design is compiled and synthesized in the Cyclone EP1C3T144C8 under the Altera Quartus II 4.2 design software. After placing and routing, the controller in the FPGA can work at the 104.46Mhz, the post simulation results show that the VHDL design is correct and the HDD controller can work correctly in the EP1C3T144C8 FPGA. The FPGA design technology used in this thesis is introduced in detail, the modules implementation and the VHDL code of the HDD controller are provided ,the timing constrain parameters are given.The work having finished in this thesis is meaningful to the data recording system design on satellite and airborne standoff. In the end, the thesis summarizes its main achivements, and gives some useful advice to the future work.