A Radar Signal Processing Asic Design

Nowadays most Radar receiver make use of DSP and FPGA to implement realtime digital signal processing. However, Compare with ASIC , the cost of DSP and FPGA is too high, and processing speed and reliability are worse. Therefore, in order to reduce the cost and increase the performance of radar system, it is necessary for radar system to research signal processing ASIC.Aim at an above-mentioned requirement, in this thesis, a radar signal processing chip is designed and researched. The main content and creative work are as follows:1.Design operation circuit of radar chip, such as, digital pulse compression, radar filter and logarithm operation. In addition, also design co-processor, clock processor and work mode.2. Synthesize RTL HDL code of radar chip into optimized gate-level netlist with SIMC 0.18um CMOS technology library. In Synthesis, make full use of various performance optimization technique.3. Complete the timing verification work of the radar chip. In timing verification, according to characteristics of the radar chip, utilize reasonably the two kinds techniques of Static Timing Analysis and Dynamic Timing Simulation.Through more than a year's time, I and my workmates had completed the design of the radar signal processing chip, and the GDSII of the chip was sent to SMIC for sign-off in Dec. 2006.