High Efficiency Research And Fpga Implementation Of High Performance Of Ldpc Codes

LDPC Code(Low-Density Parity Check Code) obtained the widespread attention because of its excellent performance which is close to the Shannon limit and its efficient iterative decoding algorithm.The parity check matrix of LDPC code is sparse, which madeits decoding complexity and the code length into linear relationship. But there is always a contradiction between the structure of LDPC parity check matrix and the code performance as well as the implementation complexity.In this thesis, a series of analysis, research and comparison has been done around the two most important factors:the structure of LDPC parity check matrix and the iterative decoding algorithm.Then chooses a kind ofpseudo random structure based on quasi-cyclic LDPC code, which has better performance,and a kind of decoding algorithm,which is convenient to realize(min_sum algorithm). Implementedthe LDPC encoder and decoderbased on FPGAplatform,which supports all kinds of definedcode length and code rate.This thesisanalyses the processing of coding and decoding,makes aneffective planning of the structure of thedecoder,anduses an optimizedalgorithm, from the perspective ofhardware implementation.Greatly reduced logical resources and improved the throughput rate,which made it in the real meaning of high performance and high efficiency.