Improvement Of Decoding Algorithm Based On LDPC Code And FPGA Implementation

Low density parity check(LDPC)codes are a class of excellent codes whose error correcting performance is close to Shannon limit.Among them,quasi cyclic LDPC(QC-LDPC)codes are a subclass of LDPC codes.A kind of LDPC codes is obtained by concatenation after cyclic shift of base matrix,which has the advantages of high performance,low complexity and parallelism.Combined with the parallel processing ability of FPGA,the decoding efficiency can be greatly improved.In this paper,QC-LDPC code as the research object,the decoding algorithm optimization of QC-LDPC code and hardware implementation based on FPGA are studied.In the aspect of decoding algorithm,aiming at the problem of over estimation of check nodes in the minimum sum decoding algorithm,two improved algorithms,adaptive minimum sum algorithm and non fixed compensation minimum sum algorithm,are proposed.In the log likelihood ratio belief propagation algorithm,the cumulative result is related to the minimum value and the second minimum value of the node side information of the input variable.The larger the difference between the two,the closer the cumulative result is to the minimum value.The adaptive minimum sum algorithm uses the difference between the minimum value and the second minimum value of the absolute value of the node side information of the input variable,and combines with the hyperbolic tangent function to propose an adaptive multiplicative factor to correct the error of the check node and improve the decoding performance.The unfixed compensation minimum sum algorithm refers to the cumulative formula in the log likelihood ratio belief propagation algorithm,and proposes an unfixed correction factor to reduce the overestimation and improve the decoding performance.Simulation results show that compared with the original algorithm,the decoding performance of the two improved algorithms is improved,the convergence speed is faster when the code is long,and the update complexity of the check node is not increased too much.In the decoder hardware design.In this paper,the overall structure design of LDPC decoder based on non fixed compensation least sum algorithm is completed,including control unit,variable node processing unit,check node processing unit,address generation module,decoding decision and parity check module.On this basis,Verilog is used for RTL level design,then vivado software of Xilinx company is used for design and simulation,and comprehensive report and sequence diagram are given.Finally,the decoder test platform is built,and the data transmission between the decoder and the host computer is realized through the PCI interface.After verifying that the function is correct,the decoder implemented in this paper is packaged into IP core,which is convenient for other users to call and shorten the development cycle.