Research On LDPC Coding Algorithm And FPGA Implementation

LDPC(Low Density Parity Check) code is a kind of linear block code that defined by very sparse parity matrix or tanner graph, and it is also called Gallager code since Gallager initially presented it. LDPC code is similar with the Turbo code, both of their performance approach Shannon limit. LDPC code has been mostly used all over the channels and become so hot in the research field of channel coding in recent years.LDPC code's parity check matrix has the characteristics of sparsp- arseness;the decoding complexity is just the linear in crease according to the code length,and this character make the application of long block code possible. Moreover, the sparse matrix makes the messages far away checked at a time, and the LDPC code can avoid the continuous bursting errors.Firstly,the paper introduces the basic conception and fundamental principle of LDPC code.Secondly,the paper introduces the structure of LDPC, all kind of encoding algorithm and produce method of generated matrix. Especially the paper introduces the structure of QC-LDPC code,RU algorithm and greedy method in detail.On the basis of RU algorithm I improve the algorithm by greedy method.Finally, I select Altera Corporation's Stratix series FPGA component EP1s25F67217 to realize the code length is 504 based on RU algorithm LDPC encoder. In the design process,in order to save resources and improve speed, I use sparse matrix technology in vector storage. I use the method of odd check Directly determine results in vector adder. In vector multiplication, I use the method of forward iteration to avoid the complex matrix inversion operation. The result indicated that this encoder only takes the approximately 10% logical unit, the approximately 5% memory cell, the clock rate achieve 120MHz, the data turnover rate achieves 33Mb/s, in the function also satisfies encoder's request.