Design And Implement Of Ldpc Decoding Algorithm Based On Fpga

In order to implement the LDPC decoder based on FPGA, many factors influencing properties of decoder have been studied in detail, such as construction of check matrix, code length, decoding algorithm, number of iterations, data quantization, etc. Firstly, we compared the computing complexity and error-correcting capability of several algorithms of LDPC decoding. Secondly, combined with the topic background, the leading parameters on the performance of LDPC decoding, such as code length, number of iterations, data quantization, etc, are analyzed with computer simulation. Finally, we gave the scheme of the hardware implement of LDPC decoders.Based on the topic background, we analyzed 3 types of decoder architecture, serial, parallel and partially parallel. The Partially-Parallel architecture of good flexible is chosen for the trade off between decoding speed and resource requirement. Base on parameters of simulation and Partially-Parallel architecture, top-level circuit and basic function partition of the LDPC decoder is given and designed by Verilog HDL language. Some verification has been executed in ISE and Modelsim, and the LDPC decoder has been implemented on FPGA.Finally, the whole test system is realized by VC. Information resource, channel and bit error rate statistics are realized by computer, LDPC encoder, LDPC decoder, MSK modulation and MSK demodulation are implementation based on FPGA. This thesis provided the whole test scheme and result. The test results indicate that LDPC decoder implementation based on FPGA has good coding performance, basically same as the theoretical coding performance.