Hardware Design And Implementation Of Vehicle Information Terminal Core Board

Vehicle information terminal is this kind of device which can not only collect the following information such as the data of the vehicle engine, car status and the location information of the vehicle, but also can store that information and transfer them to the background management platform. It also should have the capabilities of the good human-computer interaction and entertainment. The research on vehicle information terminal has been going on at home and abroad. There is a big problem in the applicability of the foreign vehicle information terminal. In addition to the problem in the usability of the vehicle, there is a serious lack of information processing capacity, the capacity of signal transmission, scalability, and rich feature of the terminal itself. The above reason results in that those terminals can not meet the relevant demand which comes from background management platform and the drivers of the vehicle. Starting from solving the problems in the domestic and foreign vehicle information terminal, the subject studies the key technology of realizing the vehicle information terminal core board as the fundamental purpose of the paper that expands as the following ideas.In connection with meeting the requirements of the vehicle information terminal, the subject aims at solving the problem that the function of vehicle information terminal is too simple and the applicability is so narrow from the perspective of enhancing the ability of information terminal information processing, collection, storage, transmission, and human-computer interaction of the terminal itself at the hardware design. And then, it puts forward the overall design of the core board of the vehicle information terminals and associated circuitry design.The design of the DDR3signal transmission link is one of the key factors which can determine whether the core board can be implemented successfully. Taking the signal integrity of high-speed digital signal such as reflection, crosstalk into account, the subject carries out a detailed analysis of the mechanism of generation of crosstalk, reflection. And then, it have done the signal integrity simulation with taking use of the related Cadence simulation tools and the IBIS model of CPU and DDR3for contrast analysis to determine the parameters of the drive output impedance, transmission line characteristics impedance, the PCB dielectric thickness, the transmission line minimum spacing which make up the transmission line link. So we can reduce the noise coming from the reflection, the crosstalk to meet the limit of DDR3noise tolerance. According to the JEDEC specification for the predetermined DDR3timing, the paper executes the detailed analysis of the mechanism for establishing and maintaining DDR3signal when we read and write the DDR3signal. At last, this paper gives corresponding relationships among the DDR3data signal drive buffer time, the transmission time of the data signal and the DDR3clock signal transmission time to guide design of DDR3transmission line. With above ways, we can settle the issues of signal integrity and timing in the DDR3signal transmission link.The issue of power integrity is another key factor to affect successful design of the core board. According to the ripple requirements of each power supply rail of the core board, the paper analyzes all aspects of the power supply system of the high-speed digital from the perspective of the power distribution network (PDN).By using the Cadence tools for the power integrity design, the paper does some comparison analysis after the simulation and gets the results that both large capacitor with large package and small capacitor with small package have the capability of reducing the power supply impedance at each frequency segment. We can determine the capacitor distribute system which enable the power supply impedance to be lower than the target impedance calculated by the ripple requirements of each power supply rail network in the frequency range from several tens KHz to several hundreds MHz, so as to solve the core board power integrity problem.After testing, from the aspect of the signal part of the core board, the DDR3signal does not have overshoot, jitter, burr and other issues, and PN two-way differential signal does not have delay. From the aspect of power part, except the DDR power supply, the peak Vp-p of the ripple of other power rails remains within30mV, and the measured peak value Vp-p of the DDR part of the power lines is113mv with the result of meeting150mV requirements from the chip manual. Finally, the LINUX kernel and the file system start normally on the hardware platform of the core system and operate stable. That proves the design of core system is successful.