Analysis And Optimization Of Signal Integrity And Power Integrity Based On AM3359 High Speed Interconnect Circuit

With the continuous breakthrough of semiconductor integrated circuit technology to more than 7nm,digital circuits are also moving towards high speed.The miniaturization of products also makes high-speed circuit design tend to be high-density and high-demand,resulting in signal integrity and power integrity problems in high-speed circuits.How to maximize the signal quality without affecting the circuit design function and effectively improve the reliability of the high-speed circuit after physicalization has gradually become an important link for researchers and engineers to consider.Therefore,it is necessary to conduct in-depth research on signal integrity and power integrity issues to meet the challenges brought by high-speed circuit design.Based on the above background,this paper designs the high-speed interconnection link module based on DDR3 and CPU in AM3359,and designs the circuit board according to the conventional layout and wiring of high-speed circuit.The IBIS model and Sigrity simulation tool are used to analyze whether the signal integrity and power integrity problems of this design meet the design index requirements,and combined with the theory to find out the method to improve the signal integrity and power integrity problems on the basis of this design.Optimize and verify.The main work is as follows:1.Based on the basic theoretical research on the characteristic impedance of transmission line,the signal integrity and power integrity are studied and analyzed in detail,and the consistency between the simulation results and the theoretical calculation results is verified by setting up a link model in Sigxplorer.Including the effect of signal reflection on amplitude;The disturbance of signal crosstalk to adjacent transmission line level and the inhibition effect of various terminal models on signal reflection.2.The IBIS files of CPU and DDR3 are analyzed.By extracting data from IBIS file models,V/I and V/T characteristic curves of different IO port models are compared and analyzed.The signal transmission quality of interconnection link address bus,data bus and clock line is simulated by Sigrity SPEED2000,a proprietary simulation tool of DDR.The compliance of the model was tested by signal reflection,overshoot and undershoot,threshold voltage,etc.The optimal model was obtained,and the accuracy of the simulation results was verified by physical tests.3.The PDN impedance of the 1.5V main power supply plane of DDR3 was analyzed,and the target impedance of the 1.5V power supply plane was calculated.Sigrity Optimize PI was used to simulate the impedance of the whole working frequency range,and the appropriate position was selected through the analysis to add decoupling capacitance to reduce the impedance of the corresponding frequency point.The power ripple noise is reduced to 47m V.The tool Sigrity Power DC was used to analyze the voltage drop from 24V-1.5V multi-power plane.In limited layout space,the voltage drop was reduced by reducing the line length or increasing the line diameter,and the current density and the current carrying capacity of the through-hole were optimized.The maximum voltage drop is 6.7m V and the maximum current density is 23.01 A/(mm~2).