Design Of A 10-Bit, 200MSample/s Analog-to-Digital Converter

During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards, such as Universal Mobile Telecommunication System, Wireless Local Area Network, Wireless Local Loop and Local Multipoint Distribution Services, has been an evolution towards higher data rate, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna. For analog-to-digital converters of radio receivers this indicates higher sample rate, wider bandwidth, higher resolution and lower power dissipation.Based on the analysis of some common high-speed ADC architectures, this thesis presents a 10-bit, 200 Msamples/s parallel pipelined ADC using TSMC 0.18μm mixed signal 1P6M CMOS process which provide metal-insulator-metal capacitor. It works at 1.8V supply voltage. This ADC is a two-channel parallel architecture. Each channel is composed of a sample-and-hold circuit, eight stages with 1.5bit per stage, and a 2 bit flash ADC as last stage. This thesis talks about the error source of pipelined ADC and calibration techniques such as digital self-calibration, analog correction and background calibration. A sample-and-hold circuit, a high-speed comparator and a MDAC component have been designed.For the purpose of raising the sample speed, we propose a parallel pipelined ADC. The key factor of parallel pipelined ADC is match between channels, which influences the effective resolution of ADC directly. We discuss the channel offset, channel gain mismatch and timing mismatch.