The Study Of The Ad Converter Of The Uhf Rfid Read-write Device And Design

In recent years, single-chip ultra high frequency(UHF) band radio frequency identification (RFID) reader is getting great improvement, which on one hand reduces the system cost and volume, and on the other hand makes the system more flexible. Due to the increasing demand for RFID system applied in handheld situation, the low power design of reader chip has become an important research issue.This work presents the whole design flow of the analog-to-digital converter in reader chip with an eye to low power application, including the analysis of system architecture, the circuit design of each module, hardware implementation and measurement.In the system design phase, the main contributions and results are:1. Based on the analysis of system requirement in single-chip UHF RFID reader, detailed design specification of the analog-to-digital converter is calculated.2. According to the design specification, considering the characteristics of different ADC types, successive approximation ADC is chosen for its low power advantage.3. After summarizing different system architectures of successive approximation ADC and comparing those pros and cons, the final scheme, which adopts top-plate sampling, fully-differential input and asynchronous timing logic, is proposed. Besides, the various non-ideal factors in this scheme are analyzed to guide circuit design, including mismatch and parasitics of capacitor array, timing constraint and circuit noise.In the circuit design phase, the main contributions and results are:4. Bootstrapped structure is adopted in the sampling switch to meet the requirement of conversion rate and linearity.5. To meet the system requirement of low voltage supply(1.2V), double tail structure is implemented in the high speed dynamic comparator design. The number of transistors between supply and ground is reduced and meanwhile, inputs and outputs are separated to decrease the kickback noise.6.asychronous timing circuits are designed to cover all the process corners so as to meet the timing constraint.In the measurement phase, the main contributions and results are:7. By contrasting the measurement results and simulation results, several assumptions are made and the main error source—dynamic offset of the comparator is discovered.8. The original comparator circuit is improved by employing preamplifier plus latch to ensure the offset voltage is constant during the comparison phase. The influence of dynamic offset turns out to be eliminated after validation based on circuit simulation.This chip is implemented using SMIC0.13um CMOS technology, the core voltage is1.2V and the core area is only0.254mm2. The measurement results demonstrate that the effective number of bit (enob) could achieve8when the input signal bandwidth is less than2MHz and the design specification is well met. Furthermore, the total power consumption of the chip is only801uW, which realizes the power optimization goal.