Design Of Analog-to-Digital Converter Based On Dynamic Vision Sensor

With the continuous development and wide application of semiconductor and integrated circuit technology,image vision sensors have developed from CCD image sensors and CMOS image sensors of the last century to today's DVS image sensors.DVS image sensor can achieve high dynamic range and high sensitivity during real-time image processing.The successive approximation analog-to-digital converter is one of the important classifications of analog-to-digital converters.Because of its low power consumption,fast response speed,and simple design,it is widely used in the information processing system of analog integrated circuits and digital-analog hybrid integrated circuits.in.This paper studies and designs the key analog-to-digital converter,SPI reference source and column readout circuit based on dynamic vision sensor.The converter adopts the function of successive approximation analog-to-digital converter to achieve performance standards such as medium accuracy,low power consumption and low noise.By building a behavior-level model,conduct behavior-level simulation of the analog-to-digital converter,and verify the function and performance of the theoretical analysis.The basic principle of the analog-to-digital converter adopts successive approximation type analog-to-digital converter and differential capacitive digital-to-analog converter to better achieve device matching,thereby reducing distortion;adopting bootstrap sampling circuit to perform distortion-free input signal Sampling to reduce the impact of charge injection of the capacitor switch and clock feedthrough effect;the comparator uses a new type of dynamic comparator and uses an output offset storage technology to reduce the offset noise of the comparator and improve the response speed;successive approximation logic control uses synchronization Clock control,internal use of new digital logic devices to reduce power consumption and simplify the design of control circuits.The SPI serial bus interface structure is used to provide reference and bias voltages for the entire pixel array and analog-to-digital converter,to ensure the output of multiple low drift,strong driving force reference and bias voltages,so that the system can be applied in harsh and complex environments in.The built-in column conversion readout module enables the multi-column pixel voltage conversion to enable priority output,prevent output conflicts,and reduce arbitration output time.This design uses the Cadence circuit design platform and the Spectre simulator.The process adopts the German XFAB 0.18 um 1P6M CIS standard process for circuit design and simulation verification of each subcircuit and the overall system of the system.The functions and performance of each sub-circuit module meet the design requirements and 9BIT analog to digital converter circuit power consumption is830 u W.The differential nonlinear error is less than ? 0.2LSB,the integral nonlinear error is less than ? 0.5LSB,the noise-to-distortion ratio is 51.74 d B,the spurious-free dynamic range is 71.99 d B,and the actual effective number of bits is 8.31.The performance indicators of the overall circuit can meet the design requirements.