Low-power Low-voltage Cmos Pipelined Touch Digital Converter Structure

The pipelined analog-to-digital converter (ADC) has become the most popular ADC architecture for high-speed and high-resolution applications which include image signal processing, digital receiver, base station, digital video, and fast Ethernet etc. In many of the applications, the reduction of power consumption is one key design issue in enhancing portability and battery operation. The trend of increasing integration level for integrated circuits has forced the ADC to reside on the same silicon with large digital circuits. By sharing the same supply voltage between ADC and digital circuit, it reduces the overhead cost for generating multiple supply voltages. Therefore, an ADC operating at the same supply voltage with the digital circuit is desirable, which forces the ADC operating at low supply voltage.This work focuses on the analysis and design of pipelined ADC for video applications especially for sub sampling applications such as digital video broadcasting over terrestrial (DVB-T) and handheld (DVB-H) systems. Emphases are placed on the analysis and design of high-performance low-power and low-voltage pipelined ADC. Architectural as well as circuital level techniques are proposed for designing high-performance low-power and low-voltage pipelined ADC.The specific research contributions of this work include(1) A new configuration is proposed in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifer (SHA) at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths, which makes the power of the ADC low and the design of the flash very simple.(2) A set of switches is proposed in the power-efficient amplifier-sharing ADC architecture to reduce the influence between the two opamp-sharing successive stages.(3) A wide-swing bias circuit is proposed for a gain-boosting telescopic amplifier to achieve a stable and high swing operation of the amplifier.(4) A symmetrical gate-bootstrapping technique with modified timing is proposed for the bottom-sampling switch of the sample-and-hold circuit to sample inputs with frequencies much above Nyquist rate.As demonstrations, the design and characterization of two experimental 10-bit, 30MS/S, CMOS pipelined ADCs are presented.