Design Of An On-Chip 10-Bit 20-Msample/s Pipilined Analog-To-Digital Conveter

With the great development of wireless communication, analog-to-digital technique, which is one of the key techniques in wireless communication, is being made amazing progress due to the higher and higher demand from products. After more than thirty years of research and development, ADCs have realized the highest precision of 24bit and the fastest speed of 40GSample/s. Various ADCs can meet the needs of nearly all applications. There are many ways in high performance ADC design, in which pipeline structure is more popular. It is because that the pipeline ADC is a good compromise between speed and precision and that its structure is more suitable for CMOS process techniques. So pipelined ADCs, one of the most popular ADCs, are mainly used in those fields which emphasize both resolution and speed, such as wireless LAN in communication, cell phone and high-resolution digital TV in custom electronic products.A 10 bit, 1.5bit per stage and 33MSPS pipeline structure ADC for transceiver of wireless LAN is designed independently. Based on the system function, the ADC is divided into some modules, including: sample-and-hold (S/H Circuit) circuit, the comparator which can compare the input signal and reference voltage, sub-DAC cell, clock, error correction and glitch eliminated circuits etc. The circuits of these modules are designed using the model of CSMC 0.6μm CMOS double poly double metal process. The design of sample-and-hold circuit is the key to realize the pipelined constraints ADC. According to the index request of the ADC, the operational–amplification (OP-amp)'s gain and bandwidth can be deduced by analyzing the error of the ADC. In addition, by using the digital correction and glitch eliminated circuits, the comparator precision requests can be relaxed (The high precision accuracy comparator usually needs to consume high power).In this design, the results of sample-and-hold circuit, the comparator which can compare the input signal and reference voltage, sub-DAC cell, clock circuits are simulated based on circuit level HSpice in Cadence with the model of 0.6μm CMOS double poly double metal process under 5 Volt single supply voltage provided by CSMC.